Modern network interface controller (NIC) devices feature multiple DMA channels connected to a host CPU over a packetized bus, e.g., HyperTransport or PCI Express. The DMA channels in these devices must share access to the CPU bus amongst themselves. Sharing is typically done fairly on a per network packet basis.
However, such implementations allow the distribution of network packet sizes to affect the proportion of CPU bus bandwidth captured by each DMA channel. Assuming the CPU bus bandwidth is oversubscribed, a DMA channel passing mostly small packets will receive much less bandwidth than a DMA channel passing mostly large packets.
If the distribution of packet sizes across each DMA channel is statistically the same, then the bandwidth distribution will even out over time, and CPU bus bandwidth sharing will be fair. However, if the DMA channels are attached to disparate applications, with widely different network packet size characteristics, then applications transiting primarily large packets will capture more of the CPU bus bandwidth than they should, therefore resulting in computational inefficiencies and disparate CPU resource distribution.